1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit which is suitable for being used in a receiver using a synthesizer system, and an IC (Integrated Circuit) for the same.
2. Description of the Related Art
When a receiver using a super-heterodyne system is configured so as to use a synthesizer system instead, in general, a local oscillation signal is outputted from a PLL circuit. FIG. 11 shows an example of such a PLL circuit 30. In the PLL circuit 30, an oscillation signal SVCO from a VCO (Voltage Controlled Oscillator) 31 is supplied to a variable frequency-dividing circuit 32. The variable frequency-dividing circuit 32 frequency-divides the oscillation signal SVCO having an oscillation frequency into a frequency-dividing signal having a frequency of 1/N (N: positive integral number) of the oscillation frequency of the oscillation signal SVCO. The resulting frequency-dividing signal is then supplied to a phase comparing circuit 33. In addition, an alternating current (A.C.) signal SREF having a reference frequency fREF is supplied to the phase comparing circuit 33.
Also, a comparison output signal from the phase comparing circuit 33 is supplied to a loop filter 35 through a charge pump circuit 34. A direct current (D.C.) voltage VC having a level which changes so as to correspond to a phase difference between the frequency of the output signal from the variable frequency-dividing circuit 32, and the reference frequency fREF is fetched from the loop filter 35. Also, the D.C. voltage VC thus fetched is supplied as a control voltage for an oscillation frequency fVCO to the VCO 31.
Therefore, in a stationary state, the oscillation frequency fVCO of the VCO 31 is given by Expression (1):fVCO=N·fREF  (1)
where N is a frequency driving ratio. Thus, the changing of the frequency-dividing ratio N makes it possible to change the oscillation frequency fVCO of the VCO 31. As a result, the oscillation signal SVCO of the VCO 31 (or a frequency-dividing signal thereof) is used as a local oscillation signal, thereby converting a frequency of a received signal. Also, the changing of the frequency-dividing ratio N makes it possible to change the frequency of the received signal. That is to say, it is possible to carry out the signal reception using the synthesizer system.
Now, in the PLL circuit 30, in the case of the same setting, the loop characteristics when the oscillation frequency fVCO is the highest frequency, and the loop characteristics when the oscillation frequency fVCO is the lowest frequency largely change from each other. Also, when the loop characteristics change, not only the stability of a feedback loop itself changes, but also a phase noise changes.
The change in phase noise results in that although the oscillation frequency fVCO of the VCO 31 should be ideally held constant, i.e., held at a value of the oscillation frequency fVCO as indicated by a heavy line in FIG. 12, the oscillation frequency fVCO of the VCO 31 changes as indicated by a thin line. Also, the phase noise is an important item in a phase of reception of a digital broadcasting, and thus exerts an influence on the reception of a broadcasting wave signal. Therefore, it is necessary to prevent the loop characteristics from changing even when the oscillation frequency fVCO changes.
On the other hand, the loop characteristics of the PLL circuit 30 depends on a transfer function G(s) when the PLL circuit 30 is held in a state of an open loop. That is to say, in FIG. 12, a signal line extending from the variable frequency-dividing circuit 32 to the phase comparing circuit 33 is cut at a point X, thereby holding the PLL circuit 30 in the open loop state. In this state, the transfer function G(s) about a signal line extending from an input terminal of the phase comparing circuit 33 (an input terminal of the reference signal SREF) to an output terminal of the variable frequency-dividing circuit 32 (an output terminal of the frequency-dividing signal) is given by Expression (2):G(s)=(ICP/2π)·(ZP(s)·KVCO)/SN  (2)
where ICP (Inductively Coupled Plasma) is a charge pump current of the charge pump circuit 34, ZP(s) is an impedance of the loop filter 35, KVCO is a control sensitivity of the VCO 31 and is given by KVCO=ΔfVCO/ΔVC, and N is a frequency-dividing ratio of the frequency-dividing circuit 32.
Therefore, when the frequency-dividing ratio N is changed for the purpose of changing the oscillation frequency fVCO, the transfer function G(s) changes accordingly. As a result, the stability and the phase noise of the PLL circuit 30 change accordingly. In addition thereto, when in a television receiver, a front end circuit is configured in the form of an IC, and the response can be made to television broadcastings of the countries by using one IC, a variability region of the oscillation frequency fVCO of the PLL circuit configured in the form of an on-chip becomes considerably wide, and the variability region of the frequency-dividing ratio N becomes considerably wide. For this reason, the stability and the phase noise of the PLL circuit 30 becomes easy to get worse.
In order to cope with this situation, it is devised as a first compensation method that reference is made to the frequency-dividing ratio N, and the charge pump current ICP of the charge pump circuit 34 is changed in proportion to the frequency-dividing ratio N thus referred, thereby suppressing the change in transfer function G(s) in Expression (2). This technique, for example, is described in Japanese Patent No. 2,842,847 and Japanese Patent Laid-Open No. 2001-156629.
In addition, a method in which since the oscillation frequency fVCO of the VCO 31 depends on an output voltage VC of the loop filter 35, that is, a control voltage VC for the VCO 31, the control voltage VC is monitored, and the charge pump current ICP is controlled in accordance with the control voltage VC is also devises as a second compensation method. This technique, for example, is described in Japanese Patent Laid-Open No. Hei 11-308101.
Moreover, the following method is also devised as a third compensation method. That is to say, in a phase of calculation of the charge pump current ICP, the PLL circuit 30 is held in the open loop state once. Also, the oscillation frequency fVCO of the VCO 31 for the control voltage VC is measured with a frequency counter, thereby actually measuring the control sensitivity KVCO. Also, the charge pump current ICP is obtained based on the control sensitivity KVCO obtained from the actual measurement result. This technique, for example, is described in non-patent literary document of “A Fully Integrated 0.13-μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer,” IEEE JSSC, pp. 967 to 982, Vol. 42, No. 5, MAY 2007.
According to the first to third compensation methods, the charge pump current ICP is changed so as to correspond to either the frequency-dividing ratio N or the oscillation frequency fVCO in Expression (2). Therefore, the transfer function G(s) can be stabilized. As a result, the loop characteristics of the PLL circuit 30 can be stabilized.